Enhancements of the CERN PCI-SCI Bridge


In the beginning of the nineteen nineties plans for the Large Hadron Collider (LHC) at the CERN/Switzerland have started. The CERN is the European Organization for Nuclear Research. The term "CERN" is an abbreviation of the French designation: Conseil Européen pour la Recherche Nucléaire. The LHC should go online soon and hopefully answers some questions regarding elementary physics and how our universe is working internally.

Anyways, one experiment within the LHC is the ATLAS experiment. This will produce lots of data that need to be moved.

Within the RD24 project at the CERN it has been evaluated how SCI (Scalable Coherent Interface) technology can be used for data transfer purposes. SCI is a high bandwidth and low latency communication system that became quite mature meanwhile (see also www.dolphinics.com). In fact, the very first PCI-to-SCI interface card has been developed by the CERN RD24 group. This card was mainly based on two FPGAs that contain all the important interface logic.

In 1997 I was a student in the Chemnitz University of Technology and in the final semesters of my computer science study. One of my professors (Wolfgang Rehm) came somehow in contact with the RD24 people and he asked me whether I'm interested in doing some analysis what we could do with this PCI-SCI bridge. Well, and I said: Ok, let's see...

The backround was that my professor dealt with parallel computing and due to its configurable FPGAs the CERN PCI-SCI bridge could perhaps be used there for communication purposes. So we got two such boards and the adventure started.
One very important feature for such an interface card is to access the memory of the machine where it is plugged in. In PCI terminology this is called PCI Master functionality. That time, this has not been implemented by the RD24 people. So I made a redesign of the so-called PCI-FPGA (which is one of two FPGAs) and implemented a PCI master.

This was the first time I got in contact with more or less high-density programmable logic devices.

The final report of this study thesis is available in the publications section.

Last modified: 23. January 2017 by Mario Trams
Email: Mario.Trams@digital-force.net